{"success":true,"data":{"pressRelease":{"id":"143945","rtpr_id":"nGNX8TyKDs-20260915","ticker":"ALAB","exchange":"NASDAQ","all_tickers":["ALAB"],"title":"Astera Labs Bolsters Leo Smart Memory Controller Family for Agentic AI and General-Purpose Cloud Workloads","author":"Globe Newswire","published_at":"2026-09-15T13:00:01.634Z","article_body":"As high-value AI applications drive explosive memory-footprint growth amid\ntight supply, new connectivity architectures enhance optimal memory\nutilization and reuse\n\nHighlights\n* New Leo X-Series optimizes token economics: Paired with Astera Labs’\nScorpio X-Series Fabric Switches, Leo X-Series enables fabric-attached memory\nfor long-context, KV-cache-intensive workloads. Platform-specific interfaces\nand customizable features improve inference performance with up to 62% faster\ntime to first token (TTFT) and up to 22% more tokens per second (TPS). [1]\n* New Leo 2 E-Series and P-Series address CPU-attached capacity and rack-scale\nmemory: The expanded Leo family supports CPU-attached DDR4 & DDR5 memory\nexpansion with PCIe® 6, single x16 and dual x8 host connectivity and CXL®\n3.2 support. The new E & P-Series Smart Memory Controllers double memory\nbandwidth and capacity versus the previous generation.\n* Reliable memory reuse improves infrastructure TCO: Hyperscale-grade RAS,\nmemory-health management, on-chip hardware engines, and automated repair\nenable reliable reuse of previously deployed DDR4 DIMMs alongside DDR5 memory\nin new, high-volume cloud server fleets.\n* Growing customer engagement and design-win momentum: The expanded Leo family\nis driving increased design activity and new design wins across a broadening\nset of AI labs, hyperscale and neocloud customers.\nSAN JOSE, Calif., Sept. 15, 2026 (GLOBE NEWSWIRE) -- Astera Labs, Inc.\n(Nasdaq: ALAB), a leader in semiconductor-based connectivity solutions for\nrack-scale AI infrastructure, today announced three new memory connectivity\nsolutions—Leo X-Series and the Leo 2 E & P-Series—extending its\nhyperscale-proven Leo Smart Memory Controller™ family\n(https://www.globenewswire.com/Tracker?data=H6D8nXZJq7Fltf3TCZIwK2skcPb60HorEJTPMuoS7V_8b3wOgG5yBT3JhiTMOFIhqdwJkANNh_bl-u46U0oh94QphItyzWpQMsPPnIOEAOn0urWs8Vzdtw65gtjWzqUJjUj3OlkIzHakNC3wFry5BqeNhlv7BzSH9ZNOWZUM5-IljS98nlfEFz2mE4BwKJ1j)\nacross direct fabric-attached GPU memory and CPU-attached expansion and\npooled/shared memory architectures.\n\n“Agentic AI adoption is outpacing the industry's ability to provision memory\nfor it, and that gap is widening every quarter,\" said Matt Kimball, vice\npresident and principal analyst at Moor Insights & Strategy. \"That growth is\nlanding at the worst possible time for memory supply, with DDR5 tight and\npricing climbing, so every gigabyte already deployed has to work harder. The\nnew Leo X-Series and Leo 2 E and P-Series Smart Memory Controllers immediately\naddress KV-cache-intensive AI workloads, improve memory utilization, and\nreliably reuse previously deployed memory across both AI and general-purpose\ncloud infrastructure, instead of simply buying more of it.\"\n\nNew Leo X-Series: direct fabric-attached memory for agentic AI\nThe new Leo X-Series is a fabric-attached Smart Memory Controller\npurpose-built to directly support AI accelerator-side memory demand. Paired\nwith Astera Labs’ Scorpio fabric switches\n(https://www.globenewswire.com/Tracker?data=0EQGPiU77RndinDCSD-lTPMmcVpogWuS_B_YBO8iD5oHG719NCqNaQLlUxbp0RYpnh6NyXaIDWVorMBrL0vsU2yjQ-3cQIT3iHtASEcN3KKwa3rjmXBbuBDO0UQYCnpGQKdblwcvqLDTa2HXZXnhV7larrLMtzIckF4p4Q28rZLIXw3wb72dFd8FGFCwg8094D5foGUW6zsESGggtl35UZgOVFK9pbGLPUo5gbkiEOZyA-VYW-w7Qfgndscr8zUIGE9eb8BoBYe_TJkPQKK6FA==),\nusing PCIe and platform-specific protocols for scaling up GPUs, Leo X-Series\nenables direct connectivity to AI fabrics and a dedicated memory tier for\noffloading KV cache and agent context. As context windows grow and multi-turn\nsessions retain more prior tokens, larger KV-cache capacity with low-latency\nand high bandwidth access becomes critical for the highest-value agentic AI\ninference workloads, helping minimize response times and deliver a more\nresponsive user experience.\n\nBy connecting memory directly to the scale-up fabric, Leo X-Series provides a\nlower-latency and higher bandwidth path for GPU-to-KV-cache access versus\narchitectures that rely solely on CPU-attached memory or NVMe storage tiers.\nLeo X-Series’ support for PCIe in addition to platform-specific custom\ninterfaces allows hyperscalers and AI platform providers to build a customized\nmemory companion architecture suited to their compute platform rather than a\none-size-fits-all design. These capabilities are designed to improve KV-cache\nperformance and token economics, delivering up to 62% lower TTFT and up to 22%\nmore TPS. [1]\n\nEnhanced Leo 2 E-Series and Leo 2 P-Series for memory expansion and\npooling/sharing\nThe enhanced Leo 2 E & P-Series provide complementary approaches to\nCPU-attached capacity and rack-scale memory utilization that can support AI\nagents, in-memory databases, and general-purpose cloud workloads. These\ndevices support four DDR4 or DDR5 memory controllers that double memory\nbandwidth and capacity versus the previous generation, while an optimized chip\npackage fits add-in cards and other designs to optimize DIMM integration\ndensity.\n* Leo 2 E-Series provides direct CPU-attached CXL 3.2 memory expansion via\nPCIe 6 x16 host connectivity. It delivers additional memory capacity without\nrequiring another CPU socket and enables infrastructure providers to redeploy\npreviously deployed memory in new, state-of-the-art cloud servers supporting\nhigh-volume workloads.\n\n\n* Leo 2 P-Series enables disaggregated CXL memory architectures with pooling\nand sharing across hosts, supported by dual-port PCIe 6 x8 connectivity and\ndynamic capacity management. Hosts can draw pooled memory on demand instead of\nover-provisioning every server, turning stranded DRAM into a rack-level\nresource increasing utilization which is critical in a memory supply\nconstrained environment.\nA common foundation for reliable, interoperable memory deployment and re-use\nAcross the Leo family, hyperscale-grade RAS and memory-health management\nsupport reliable operation for evolving compute and memory platforms.\nPurpose-built memory test engines and automated repair engines help extend\nmaximum lifetime for existing memory DIMMs, assist with pre-deployment\ntesting, and identify reliable DIMMs for reuse. Enhanced memory error\nreporting, event recording, scrubbing, customizable thermal management, and\nresilient firmware updates help protect workloads and extend memory service\nlife. Workload monitoring, performance profiling, hotness tracking,\nsoftware-defined data placement, and latency optimization help fine-tune\nmemory placement and access latency for long-context agentic AI and general\npurpose workloads. Telemetry and management integration, together with Astera\nLabs’ COSMOS software suite, provides fleet-wide visibility as operators\ncombine previously deployed DDR4, newly deployed DDR5 in modern cloud server\nfleets, pooled, and accelerator-attached capacity across the rack.\n\n“Agentic AI is where the economics of AI infrastructure are being decided,\nand those economics depend on putting every usable gigabyte of memory to\nwork,” said Thad Omura, senior vice president, Compute Connectivity Group at\nAstera Labs. “The enhanced Leo family gives infrastructure providers\npurpose-built ways to connect memory to accelerators, CPUs, and hosts across\nthe rack—turning previously deployed and stranded capacity into a resource\nthat new AI and cloud workloads can use. We're seeing that translate into\nbroader customer engagement across AI labs, hyperscalers, and neoclouds.”\n\nThe enhanced Leo family was developed by Astera Labs in close collaboration\nwith CPU and GPU ecosystem partners, including AMD, Arm, Intel, and major\nmemory suppliers, alongside additional hyperscale and OEM collaborators. The\nfamily is sampling today with hyperscaler customers.\n\nAstera Labs will demonstrate Leo family capabilities—including direct\nfabric-attached memory for Agentic AI, DDR4 reuse, dynamic memory pooling, and\nAgentic AI memory tiering with Scorpio X-Series—at AI Infra Summit 2026\n(https://www.globenewswire.com/Tracker?data=CwAwCNa37x74RM12Kayi1UCFR7mdOhDOiO-856nr3TiyO-Gv1rS1iYxYGotiAItqbkO1et6zYoum-RD6YMfmttDz2GY9Mjrptl0Ea2JDmcs=)\nat the Santa Clara Convention Center, September 15–17.\n\nAdditional Resources:\n* Leo Smart Memory Controllers webpage:\nhttps://www.asteralabs.com/products/leo-smart-memory-controllers/ \n* “Supercharging Agentic AI: How Leo X-Series Smart Memory Controllers\nAccelerate Inference With KV Cache Offload” blog:\nwww.asteralabs.com/resources/blog/supercharging-agentic-ai-how-leo-x-series-smart-memory-controllers-accelerate-inference-with-kv-cache-offload/\nEcosystem Support:\nRobert Hormuth, corporate vice president, Architecture and Strategy at AMD,\nsaid:\n“Agentic AI is increasing demand for balanced systems that can move and\nprocess more data without sacrificing efficiency. AMD EPYC processors deliver\nleadership performance, exceptional memory bandwidth and capacity, and\nhigh-speed I/O across the broadly deployed x86 platform. Our collaboration\nwith Astera Labs around CXL extends that foundation, giving customers greater\nflexibility to scale memory-intensive AI and cloud workloads and improve\ninfrastructure utilization.”\n\nEddie Ramirez, Vice President of Go-To-Market, Cloud AI, Arm, said:\n“As AI infrastructure evolves, agentic AI, reinforcement learning and\ndatabase workloads are driving demand for higher-capacity memory. Arm\nand Astera Labs are working together to pair Arm AGI CPU with Leo CXL Smart\nMemory Controllers, helping customers meet these growing requirements while\nmaintaining scalable performance.”\n\nSrini Krishna, Fellow at Intel Data Center Group, said:\n\"CXL was created to bring greater flexibility and efficiency to memory across\nthe data center. Technologies like Astera Labs' Leo Smart Memory Controllers\nhelp turn that vision into reality, demonstrating how ecosystem innovation can\nhelp customers get more out of their AI infrastructure and support the next\ngeneration of data-intensive workloads.\"\n\nJangseok Choi, Vice President of Product Planning Team at Samsung Electronics,\nsaid:\n\"We are contributing to the evolution of AI infrastructure through the\ndevelopment of CXL memory solutions designed to help address the growing\nmemory demands of modern data centers. We are excited to collaborate with\nAstera Labs to help ensure our DRAM solution offer strong interoperability\nwithin the evolving CXL ecosystem, and remain committed to supporting a\nscalable, high-performance memory architecture for the AI era.\"\n\nAbout Astera Labs\nAstera Labs (Nasdaq: ALAB) provides rack-scale AI infrastructure through\npurpose-built connectivity solutions. By collaborating with hyperscalers and\necosystem partners, Astera Labs enables organizations to unlock the full\npotential of modern AI. Astera Labs’ Intelligent Connectivity Platform\nintegrates CXL®, Ethernet, NVLink Fusion, PCIe®, and UALink™\nsemiconductor-based technologies with the company’s COSMOS software suite to\nunify diverse components into cohesive, flexible systems that deliver\nend-to-end scale-up and scale-out connectivity. The company’s custom\nconnectivity solutions business complements its standards-based portfolio,\nenabling customers to deploy tailored architectures to meet their unique\ninfrastructure requirements. Discover more at www.asteralabs.com.\n\n[1] As measured by Astera Labs internal testing on an Intel GNR server with 8\nDDR5 memory channels populated, using a data center Gen 5 AI accelerator on\nthe Qwen2.5-32B AI Model. \n\nForward-Looking Statements\nThis communication contains forward-looking statements within the meaning of\nthe federal securities laws, including statements regarding the expected\ncapabilities, performance, benefits, availability, customer adoption,\ncommercial success and market opportunity of Astera Labs' expanded Leo Smart\nMemory Controller family of products, as well as related market trends and\nconditions. Forward-looking statements may be identified by words such as\n“allows,” “built to,” “can,” “climbing,” “could,”\n“designed,” “growth,” “vision,” “will” and similar\nexpressions.\n\nThese forward-looking statements are based on current expectations and\nassumptions and involve risks and uncertainties that could cause actual\nresults to differ materially from those expressed or implied by such\nstatements. These risks and uncertainties include, among others, the risk that\ndemand for agentic AI, AI inference, memory-intensive workloads and related\ninfrastructure does not develop as anticipated; memory market conditions,\nincluding supply, availability and pricing trends, do not evolve as expected;\ncustomers do not adopt CXL, fabric-attached memory, memory pooling, sharing,\nexpansion or other next-generation memory architectures; Astera Labs' products\ndo not achieve the expected performance, utilization, reliability,\ninteroperability, memory reuse, infrastructure efficiency or economic benefits\nin customer environments; benchmark, testing or simulation results are not\nindicative of real-world performance; customer evaluations, engagements,\ndesign activity, design wins or sampling programs do not result in production\ndeployments or revenue; Astera Labs and its ecosystem partners are unable to\ndevelop, manufacture, qualify, deploy or support products and technologies on\nexpected timelines or at expected cost; changes in technology, customer\nrequirements, competitive offerings or industry standards; supply chain\nconstraints or disruptions; litigation or disputes relating to our products or\ntechnologies; global economic, political and industry conditions, including\nthose affecting the semiconductor and AI infrastructure markets; regulatory\ndevelopments; international conflicts; and other risks and uncertainties\ndescribed in Astera Labs' Annual Report on Form 10-K, Quarterly Reports on\nForm 10-Q and other filings with the Securities and Exchange Commission.\n\nForward-looking statements speak only as of the date they are made. Readers\nare cautioned not to place undue reliance on forward-looking statements, and\nAstera Labs undertakes no obligation to update or revise any forward-looking\nstatement, whether as a result of new information, future events or otherwise,\nexcept as required by law.\n\nMedia Contact:\nPeter Lo\nPeter.lo@asteralabs.com \n\n(https://www.globenewswire.com/NewsRoom/AttachmentNg/2c06b09e-7cf8-4c27-99c0-84ca5ea62af5)\n\n\n\nGlobeNewswire, Inc. 2026","article_body_html":"","raw_payload":{"data":{"id":"nGNX8TyKDs-20260915","title":"Astera Labs Bolsters Leo Smart Memory Controller Family for Agentic AI and General-Purpose Cloud Workloads","author":"Globe Newswire","ticker":"ALAB","created":"2026-09-15T13:00:01.634Z","tickers":["ALAB"],"exchange":"NASDAQ","article_body":"As high-value AI applications drive explosive memory-footprint growth amid\ntight supply, new connectivity architectures enhance optimal memory\nutilization and reuse\n\nHighlights\n* New Leo X-Series optimizes token economics: Paired with Astera Labs’\nScorpio X-Series Fabric Switches, Leo X-Series enables fabric-attached memory\nfor long-context, KV-cache-intensive workloads. Platform-specific interfaces\nand customizable features improve inference performance with up to 62% faster\ntime to first token (TTFT) and up to 22% more tokens per second (TPS). [1]\n* New Leo 2 E-Series and P-Series address CPU-attached capacity and rack-scale\nmemory: The expanded Leo family supports CPU-attached DDR4 & DDR5 memory\nexpansion with PCIe® 6, single x16 and dual x8 host connectivity and CXL®\n3.2 support. The new E & P-Series Smart Memory Controllers double memory\nbandwidth and capacity versus the previous generation.\n* Reliable memory reuse improves infrastructure TCO: Hyperscale-grade RAS,\nmemory-health management, on-chip hardware engines, and automated repair\nenable reliable reuse of previously deployed DDR4 DIMMs alongside DDR5 memory\nin new, high-volume cloud server fleets.\n* Growing customer engagement and design-win momentum: The expanded Leo family\nis driving increased design activity and new design wins across a broadening\nset of AI labs, hyperscale and neocloud customers.\nSAN JOSE, Calif., Sept. 15, 2026 (GLOBE NEWSWIRE) -- Astera Labs, Inc.\n(Nasdaq: ALAB), a leader in semiconductor-based connectivity solutions for\nrack-scale AI infrastructure, today announced three new memory connectivity\nsolutions—Leo X-Series and the Leo 2 E & P-Series—extending its\nhyperscale-proven Leo Smart Memory Controller™ family\n(https://www.globenewswire.com/Tracker?data=H6D8nXZJq7Fltf3TCZIwK2skcPb60HorEJTPMuoS7V_8b3wOgG5yBT3JhiTMOFIhqdwJkANNh_bl-u46U0oh94QphItyzWpQMsPPnIOEAOn0urWs8Vzdtw65gtjWzqUJjUj3OlkIzHakNC3wFry5BqeNhlv7BzSH9ZNOWZUM5-IljS98nlfEFz2mE4BwKJ1j)\nacross direct fabric-attached GPU memory and CPU-attached expansion and\npooled/shared memory architectures.\n\n“Agentic AI adoption is outpacing the industry's ability to provision memory\nfor it, and that gap is widening every quarter,\" said Matt Kimball, vice\npresident and principal analyst at Moor Insights & Strategy. \"That growth is\nlanding at the worst possible time for memory supply, with DDR5 tight and\npricing climbing, so every gigabyte already deployed has to work harder. The\nnew Leo X-Series and Leo 2 E and P-Series Smart Memory Controllers immediately\naddress KV-cache-intensive AI workloads, improve memory utilization, and\nreliably reuse previously deployed memory across both AI and general-purpose\ncloud infrastructure, instead of simply buying more of it.\"\n\nNew Leo X-Series: direct fabric-attached memory for agentic AI\nThe new Leo X-Series is a fabric-attached Smart Memory Controller\npurpose-built to directly support AI accelerator-side memory demand. Paired\nwith Astera Labs’ Scorpio fabric switches\n(https://www.globenewswire.com/Tracker?data=0EQGPiU77RndinDCSD-lTPMmcVpogWuS_B_YBO8iD5oHG719NCqNaQLlUxbp0RYpnh6NyXaIDWVorMBrL0vsU2yjQ-3cQIT3iHtASEcN3KKwa3rjmXBbuBDO0UQYCnpGQKdblwcvqLDTa2HXZXnhV7larrLMtzIckF4p4Q28rZLIXw3wb72dFd8FGFCwg8094D5foGUW6zsESGggtl35UZgOVFK9pbGLPUo5gbkiEOZyA-VYW-w7Qfgndscr8zUIGE9eb8BoBYe_TJkPQKK6FA==),\nusing PCIe and platform-specific protocols for scaling up GPUs, Leo X-Series\nenables direct connectivity to AI fabrics and a dedicated memory tier for\noffloading KV cache and agent context. As context windows grow and multi-turn\nsessions retain more prior tokens, larger KV-cache capacity with low-latency\nand high bandwidth access becomes critical for the highest-value agentic AI\ninference workloads, helping minimize response times and deliver a more\nresponsive user experience.\n\nBy connecting memory directly to the scale-up fabric, Leo X-Series provides a\nlower-latency and higher bandwidth path for GPU-to-KV-cache access versus\narchitectures that rely solely on CPU-attached memory or NVMe storage tiers.\nLeo X-Series’ support for PCIe in addition to platform-specific custom\ninterfaces allows hyperscalers and AI platform providers to build a customized\nmemory companion architecture suited to their compute platform rather than a\none-size-fits-all design. These capabilities are designed to improve KV-cache\nperformance and token economics, delivering up to 62% lower TTFT and up to 22%\nmore TPS. [1]\n\nEnhanced Leo 2 E-Series and Leo 2 P-Series for memory expansion and\npooling/sharing\nThe enhanced Leo 2 E & P-Series provide complementary approaches to\nCPU-attached capacity and rack-scale memory utilization that can support AI\nagents, in-memory databases, and general-purpose cloud workloads. These\ndevices support four DDR4 or DDR5 memory controllers that double memory\nbandwidth and capacity versus the previous generation, while an optimized chip\npackage fits add-in cards and other designs to optimize DIMM integration\ndensity.\n* Leo 2 E-Series provides direct CPU-attached CXL 3.2 memory expansion via\nPCIe 6 x16 host connectivity. It delivers additional memory capacity without\nrequiring another CPU socket and enables infrastructure providers to redeploy\npreviously deployed memory in new, state-of-the-art cloud servers supporting\nhigh-volume workloads.\n\n\n* Leo 2 P-Series enables disaggregated CXL memory architectures with pooling\nand sharing across hosts, supported by dual-port PCIe 6 x8 connectivity and\ndynamic capacity management. Hosts can draw pooled memory on demand instead of\nover-provisioning every server, turning stranded DRAM into a rack-level\nresource increasing utilization which is critical in a memory supply\nconstrained environment.\nA common foundation for reliable, interoperable memory deployment and re-use\nAcross the Leo family, hyperscale-grade RAS and memory-health management\nsupport reliable operation for evolving compute and memory platforms.\nPurpose-built memory test engines and automated repair engines help extend\nmaximum lifetime for existing memory DIMMs, assist with pre-deployment\ntesting, and identify reliable DIMMs for reuse. Enhanced memory error\nreporting, event recording, scrubbing, customizable thermal management, and\nresilient firmware updates help protect workloads and extend memory service\nlife. Workload monitoring, performance profiling, hotness tracking,\nsoftware-defined data placement, and latency optimization help fine-tune\nmemory placement and access latency for long-context agentic AI and general\npurpose workloads. Telemetry and management integration, together with Astera\nLabs’ COSMOS software suite, provides fleet-wide visibility as operators\ncombine previously deployed DDR4, newly deployed DDR5 in modern cloud server\nfleets, pooled, and accelerator-attached capacity across the rack.\n\n“Agentic AI is where the economics of AI infrastructure are being decided,\nand those economics depend on putting every usable gigabyte of memory to\nwork,” said Thad Omura, senior vice president, Compute Connectivity Group at\nAstera Labs. “The enhanced Leo family gives infrastructure providers\npurpose-built ways to connect memory to accelerators, CPUs, and hosts across\nthe rack—turning previously deployed and stranded capacity into a resource\nthat new AI and cloud workloads can use. We're seeing that translate into\nbroader customer engagement across AI labs, hyperscalers, and neoclouds.”\n\nThe enhanced Leo family was developed by Astera Labs in close collaboration\nwith CPU and GPU ecosystem partners, including AMD, Arm, Intel, and major\nmemory suppliers, alongside additional hyperscale and OEM collaborators. The\nfamily is sampling today with hyperscaler customers.\n\nAstera Labs will demonstrate Leo family capabilities—including direct\nfabric-attached memory for Agentic AI, DDR4 reuse, dynamic memory pooling, and\nAgentic AI memory tiering with Scorpio X-Series—at AI Infra Summit 2026\n(https://www.globenewswire.com/Tracker?data=CwAwCNa37x74RM12Kayi1UCFR7mdOhDOiO-856nr3TiyO-Gv1rS1iYxYGotiAItqbkO1et6zYoum-RD6YMfmttDz2GY9Mjrptl0Ea2JDmcs=)\nat the Santa Clara Convention Center, September 15–17.\n\nAdditional Resources:\n* Leo Smart Memory Controllers webpage:\nhttps://www.asteralabs.com/products/leo-smart-memory-controllers/ \n* “Supercharging Agentic AI: How Leo X-Series Smart Memory Controllers\nAccelerate Inference With KV Cache Offload” blog:\nwww.asteralabs.com/resources/blog/supercharging-agentic-ai-how-leo-x-series-smart-memory-controllers-accelerate-inference-with-kv-cache-offload/\nEcosystem Support:\nRobert Hormuth, corporate vice president, Architecture and Strategy at AMD,\nsaid:\n“Agentic AI is increasing demand for balanced systems that can move and\nprocess more data without sacrificing efficiency. AMD EPYC processors deliver\nleadership performance, exceptional memory bandwidth and capacity, and\nhigh-speed I/O across the broadly deployed x86 platform. Our collaboration\nwith Astera Labs around CXL extends that foundation, giving customers greater\nflexibility to scale memory-intensive AI and cloud workloads and improve\ninfrastructure utilization.”\n\nEddie Ramirez, Vice President of Go-To-Market, Cloud AI, Arm, said:\n“As AI infrastructure evolves, agentic AI, reinforcement learning and\ndatabase workloads are driving demand for higher-capacity memory. Arm\nand Astera Labs are working together to pair Arm AGI CPU with Leo CXL Smart\nMemory Controllers, helping customers meet these growing requirements while\nmaintaining scalable performance.”\n\nSrini Krishna, Fellow at Intel Data Center Group, said:\n\"CXL was created to bring greater flexibility and efficiency to memory across\nthe data center. Technologies like Astera Labs' Leo Smart Memory Controllers\nhelp turn that vision into reality, demonstrating how ecosystem innovation can\nhelp customers get more out of their AI infrastructure and support the next\ngeneration of data-intensive workloads.\"\n\nJangseok Choi, Vice President of Product Planning Team at Samsung Electronics,\nsaid:\n\"We are contributing to the evolution of AI infrastructure through the\ndevelopment of CXL memory solutions designed to help address the growing\nmemory demands of modern data centers. We are excited to collaborate with\nAstera Labs to help ensure our DRAM solution offer strong interoperability\nwithin the evolving CXL ecosystem, and remain committed to supporting a\nscalable, high-performance memory architecture for the AI era.\"\n\nAbout Astera Labs\nAstera Labs (Nasdaq: ALAB) provides rack-scale AI infrastructure through\npurpose-built connectivity solutions. By collaborating with hyperscalers and\necosystem partners, Astera Labs enables organizations to unlock the full\npotential of modern AI. Astera Labs’ Intelligent Connectivity Platform\nintegrates CXL®, Ethernet, NVLink Fusion, PCIe®, and UALink™\nsemiconductor-based technologies with the company’s COSMOS software suite to\nunify diverse components into cohesive, flexible systems that deliver\nend-to-end scale-up and scale-out connectivity. The company’s custom\nconnectivity solutions business complements its standards-based portfolio,\nenabling customers to deploy tailored architectures to meet their unique\ninfrastructure requirements. Discover more at www.asteralabs.com.\n\n[1] As measured by Astera Labs internal testing on an Intel GNR server with 8\nDDR5 memory channels populated, using a data center Gen 5 AI accelerator on\nthe Qwen2.5-32B AI Model. \n\nForward-Looking Statements\nThis communication contains forward-looking statements within the meaning of\nthe federal securities laws, including statements regarding the expected\ncapabilities, performance, benefits, availability, customer adoption,\ncommercial success and market opportunity of Astera Labs' expanded Leo Smart\nMemory Controller family of products, as well as related market trends and\nconditions. Forward-looking statements may be identified by words such as\n“allows,” “built to,” “can,” “climbing,” “could,”\n“designed,” “growth,” “vision,” “will” and similar\nexpressions.\n\nThese forward-looking statements are based on current expectations and\nassumptions and involve risks and uncertainties that could cause actual\nresults to differ materially from those expressed or implied by such\nstatements. These risks and uncertainties include, among others, the risk that\ndemand for agentic AI, AI inference, memory-intensive workloads and related\ninfrastructure does not develop as anticipated; memory market conditions,\nincluding supply, availability and pricing trends, do not evolve as expected;\ncustomers do not adopt CXL, fabric-attached memory, memory pooling, sharing,\nexpansion or other next-generation memory architectures; Astera Labs' products\ndo not achieve the expected performance, utilization, reliability,\ninteroperability, memory reuse, infrastructure efficiency or economic benefits\nin customer environments; benchmark, testing or simulation results are not\nindicative of real-world performance; customer evaluations, engagements,\ndesign activity, design wins or sampling programs do not result in production\ndeployments or revenue; Astera Labs and its ecosystem partners are unable to\ndevelop, manufacture, qualify, deploy or support products and technologies on\nexpected timelines or at expected cost; changes in technology, customer\nrequirements, competitive offerings or industry standards; supply chain\nconstraints or disruptions; litigation or disputes relating to our products or\ntechnologies; global economic, political and industry conditions, including\nthose affecting the semiconductor and AI infrastructure markets; regulatory\ndevelopments; international conflicts; and other risks and uncertainties\ndescribed in Astera Labs' Annual Report on Form 10-K, Quarterly Reports on\nForm 10-Q and other filings with the Securities and Exchange Commission.\n\nForward-looking statements speak only as of the date they are made. Readers\nare cautioned not to place undue reliance on forward-looking statements, and\nAstera Labs undertakes no obligation to update or revise any forward-looking\nstatement, whether as a result of new information, future events or otherwise,\nexcept as required by law.\n\nMedia Contact:\nPeter Lo\nPeter.lo@asteralabs.com \n\n(https://www.globenewswire.com/NewsRoom/AttachmentNg/2c06b09e-7cf8-4c27-99c0-84ca5ea62af5)\n\n\n\nGlobeNewswire, Inc. 2026"},"type":"article","timestamp":"2026-09-15T13:00:02.364461968Z","server_sent_at_ms":1789477202364},"received_at":"2026-09-15T13:00:19.429Z","source_url":null},"analysis":{"id":"132777","press_release_id":"143945","analysis_json":{"industry":{"label":"Semiconductors & Semiconductor Equipment","sector":"Information Technology"},"redFlags":["Performance claims (62% TTFT, 22% TPS) are based on Astera Labs internal testing, not independent third-party benchmarks","Design wins and sampling programs may not convert to production deployments or revenue (company's own forward-looking risk disclosure)"],"eventType":"product_launch","narrative":"Astera Labs unveiled three new memory connectivity solutions — the Leo X-Series and Leo 2 E & P-Series — extending its Leo Smart Memory Controller family across fabric-attached GPU memory, CPU-attached expansion, and pooled/shared rack-scale memory architectures.\n\nThe Leo X-Series, paired with Scorpio X-Series fabric switches, targets KV-cache-intensive agentic AI inference with claimed gains of up to 62% faster time to first token and up to 22% more tokens per second, while the Leo 2 E & P-Series double memory bandwidth and capacity versus the prior generation with PCIe 6 and CXL 3.2 support.\n\nThe family is sampling with hyperscaler customers today, and management cites growing design wins across AI labs, hyperscalers, and neoclouds, with ecosystem support from AMD, Arm, Intel, and Samsung.\n\nStrategically, the products aim at a memory-supply-constrained environment by enabling DDR4 reuse, memory pooling, and higher utilization — an infrastructure TCO pitch that supports Astera Labs' rack-scale AI connectivity roadmap.","sentiment":"bullish","agentHooks":{"shouldPost":true,"suggestedAngle":"Astera Labs attacks the agentic AI memory bottleneck with quantified token-economics gains and hyperscaler sampling — watch for design-win conversion into Leo-family revenue."},"keyFigures":{"customDimensions":{"tps_improvement":"up to 22%","ttft_improvement":"up to 62%","interconnect_support":"PCIe 6, CXL 3.2","memory_capacity_vs_prior_gen":"2x","memory_bandwidth_vs_prior_gen":"2x"}},"quotedText":"Agentic AI is where the economics of AI infrastructure are being decided, and those economics depend on putting every usable gigabyte of memory to work","namedEntities":{"people":[{"name":"Thad Omura","role":"Senior Vice President, Compute Connectivity Group, Astera Labs"},{"name":"Matt Kimball","role":"Vice President and Principal Analyst, Moor Insights & Strategy"},{"name":"Robert Hormuth","role":"Corporate Vice President, Architecture and Strategy, AMD"},{"name":"Eddie Ramirez","role":"Vice President of Go-To-Market, Cloud AI, Arm"},{"name":"Srini Krishna","role":"Fellow, Intel Data Center Group"},{"name":"Jangseok Choi","role":"Vice President of Product Planning Team, Samsung Electronics"},{"name":"Peter Lo","role":"Media Contact, Astera Labs"}],"products":["Leo X-Series Smart Memory Controller","Leo 2 E-Series Smart Memory Controller","Leo 2 P-Series Smart Memory Controller","Scorpio X-Series Fabric Switches","COSMOS software suite","AMD EPYC processors","Arm AGI CPU","Qwen2.5-32B AI Model"],"companies":[{"name":"Astera Labs, Inc.","ticker":"ALAB","relationship":"filer"},{"name":"Moor Insights & Strategy","relationship":"analyst firm quoted"},{"name":"AMD","relationship":"ecosystem partner (CPU)"},{"name":"Arm","relationship":"ecosystem partner (CPU)"},{"name":"Intel","relationship":"ecosystem partner (CPU)"},{"name":"Samsung Electronics","relationship":"memory supplier partner"}],"dollarAmounts":[]},"materialImpact":{"score":3,"reasoning":"Major expansion of the Leo Smart Memory Controller family (Leo X-Series, Leo 2 E & P-Series) that is already sampling with hyperscaler customers, with quantified performance claims (up to 62% faster TTFT, up to 22% more TPS) and cited design-win momentum across AI labs, hyperscalers, and neoclouds. Meaningful to the product roadmap and future revenue, but still a product announcement with no financial figures or revenue quantification."},"tickerRelevance":{"others":[],"primary":"ALAB"},"globalImportance":30,"audienceRelevance":45,"eventTypeSecondary":[],"importanceComponents":{"tickerTier":"mid-cap AI-infrastructure semiconductor name with strong retail following","eventGravity":"product-family expansion, sampling with hyperscalers, design-win claims but no financials","sectorWeight":"high — AI connectivity/memory is a hot theme","benchmarkBasis":"vendor internal testing only, limits claim credibility","retailFavoriteBoost":"moderate — ALAB is a retail-favorite AI infrastructure stock","revenueQuantification":"none disclosed"}},"event_type":"product_launch","event_type_secondary":null,"sentiment":"bullish","material_impact_score":3,"narrative":"Astera Labs unveiled three new memory connectivity solutions — the Leo X-Series and Leo 2 E & P-Series — extending its Leo Smart Memory Controller family across fabric-attached GPU memory, CPU-attached expansion, and pooled/shared rack-scale memory architectures.\n\nThe Leo X-Series, paired with Scorpio X-Series fabric switches, targets KV-cache-intensive agentic AI inference with claimed gains of up to 62% faster time to first token and up to 22% more tokens per second, while the Leo 2 E & P-Series double memory bandwidth and capacity versus the prior generation with PCIe 6 and CXL 3.2 support.\n\nThe family is sampling with hyperscaler customers today, and management cites growing design wins across AI labs, hyperscalers, and neoclouds, with ecosystem support from AMD, Arm, Intel, and Samsung.\n\nStrategically, the products aim at a memory-supply-constrained environment by enabling DDR4 reuse, memory pooling, and higher utilization — an infrastructure TCO pitch that supports Astera Labs' rack-scale AI connectivity roadmap.","key_figures":{"customDimensions":{"tps_improvement":"up to 22%","ttft_improvement":"up to 62%","interconnect_support":"PCIe 6, CXL 3.2","memory_capacity_vs_prior_gen":"2x","memory_bandwidth_vs_prior_gen":"2x"}},"named_entities":{"people":[{"name":"Thad Omura","role":"Senior Vice President, Compute Connectivity Group, Astera Labs"},{"name":"Matt Kimball","role":"Vice President and Principal Analyst, Moor Insights & Strategy"},{"name":"Robert Hormuth","role":"Corporate Vice President, Architecture and Strategy, AMD"},{"name":"Eddie Ramirez","role":"Vice President of Go-To-Market, Cloud AI, Arm"},{"name":"Srini Krishna","role":"Fellow, Intel Data Center Group"},{"name":"Jangseok Choi","role":"Vice President of Product Planning Team, Samsung Electronics"},{"name":"Peter Lo","role":"Media Contact, Astera Labs"}],"products":["Leo X-Series Smart Memory Controller","Leo 2 E-Series Smart Memory Controller","Leo 2 P-Series Smart Memory Controller","Scorpio X-Series Fabric Switches","COSMOS software suite","AMD EPYC processors","Arm AGI CPU","Qwen2.5-32B AI Model"],"companies":[{"name":"Astera Labs, Inc.","ticker":"ALAB","relationship":"filer"},{"name":"Moor Insights & Strategy","relationship":"analyst firm quoted"},{"name":"AMD","relationship":"ecosystem partner (CPU)"},{"name":"Arm","relationship":"ecosystem partner (CPU)"},{"name":"Intel","relationship":"ecosystem partner (CPU)"},{"name":"Samsung Electronics","relationship":"memory supplier partner"}],"dollarAmounts":[]},"model_name":"glm-5.3-flash","prompt_hash":"sha256:727b4b9429a443af","schema_hash":"sha256:05005c02d9cffac9","created_at":"2026-09-15T13:01:59.886Z","global_importance":30,"audience_relevance":45,"importance_components":{"tickerTier":"mid-cap AI-infrastructure semiconductor name with strong retail following","eventGravity":"product-family expansion, sampling with hyperscalers, design-win claims but no financials","sectorWeight":"high — AI connectivity/memory is a hot theme","benchmarkBasis":"vendor internal testing only, limits claim credibility","retailFavoriteBoost":"moderate — ALAB is a retail-favorite AI infrastructure stock","revenueQuantification":"none disclosed"}},"durationMs":36367,"modelName":"glm-5.3-flash"}}